The present invention relates generally to communications on a single chip, and more particularly, to a bidirectional bus repeater for communicating on a single chip.
Address and data busses provide data paths that are shared by a number of data processing devices, such as memory devices, micro-controllers, microprocessors, digital signal processors (DSPs) and peripheral devices. Busses are typically formed on printed circuit boards (PCBs) and interconnect the various devices mounted on the PCB. The busses may also extend to connectors in order to allow external devices to be coupled to the bus.
Recently, integrated circuit (IC) manufacturers have begun producing single chips containing multiple device cores, such as multiple memory devices, micro-controllers, microprocessors and digital signal processors (DSPs), that were traditionally mounted on a PCB and interconnected by one or more busses on the PCB. Such a single chip is commonly referred to as a system-on-a-chip (SoC). SoCs incorporate one or more busses to provide data paths to interconnect the multiple core devices on the chip, often referred to as xe2x80x9cnodes.xe2x80x9d The busses on SoCs, however, comprise conductor traces on the chip and thus tend to be much shorter in length and less sensitive to noise than PC3 busses.
As SoCs grow in size and complexity, the requirement of communicating control and data signals between various nodes or devices on the SoC becomes more difficult. To meet customer expectations for increasing performance, the busses for communicating address and data signals are required to transfer data at the speed of the system clock. Most currently available SoCs provide high-speed unidirectional buses with cross switches or multiplexers for connecting different nodes, since a unidirectional bus usually provides a faster bus transfer rate. While the unidirectional buses provide the required transfer rates, they require additional control signals for the cross switches, as well as additional area for routing the multiplicity of buses, which is not practical for SoC applications. Furthermore, the bus architecture requires a clear distinction of master nodes, such as processors, from slave nodes, such as memories. This distinction prevents any direct data transfer from one master device to another master device or a transfer from one slave device to another slave device. Thus, additional operation cycles are required to perform a direct memory access (DMA) operation.
A bidirectional bus could overcome some of the identified disadvantages of a unidirectional bus. One of the main problems associated with a bidirectional bus, however, is that there has been no clear way of preventing the dispersion of a signal waveform on the bus. Generally, for a unidirectional bus, a repeater reshapes the signal waveform and also reduces the resistive-capacitive (RC) delays on the bus by segmenting the bus wire with a number of repeaters inserted at strategic locations on the bus. This approach has not been possible for a bidirectional bus, however, since, by nature, a repeater is a unidirectional element. Thus, any node connected to a bus on the output side of a repeater can only drive the bus with an unacceptable delay (or rise/fall time), if at all.
A need therefore exists for a high-speed bidirectional bus for use in integrated circuits, such as SoC devices or printed circuit boards (PCBs). A further need exists for a bidirectional repeater circuit that can reduce dispersion of a signal waveform, while also reducing the RC delay on the bus by segmenting long bus wires.
Generally, a bidirectional bus repeater is disclosed that connects individual segments of a bidirectional bus. The exemplary bidirectional bus repeater consists of a direction control block and a buffer block. The buffer block contains one pair of buffers for each bus bit and an extra pair associated with the indicator lines. Indicator lines are used by the direction control block based on activity on the bus to generate control signals (control-A and control-B) that control the state of the tri-state buffers. In an exemplary embodiment, each node must toggle the indicator line whenever the node drives the bus.
When the bus is inactive, the control-A and control-B signals generated by the direction control block are both inactive because the voltages on both sides of the bidirectional bus repeater are the same. When the direction control block detects a change of voltage on the indicator line associated with one side of the bus (e.g., indicator-A associated with bus-A), the corresponding tri-state buffers are enabled. Thereafter, the opposite bus segment (bus-B) is driven by the repeater buffers, until the bus segment bus-B reaches the same logic level as the bus segment bus-A. The logic level on indicator-B also changes to the same logic level as indicator-A. Eventually, both segments of the bus wire and the indicator wires connected to the bidirectional bus repeater circuit are equal and the DC turns off the control signal A (cntl-A).
The bidirectional bus repeater of the present invention is guided by the bus signals themselves and thus does not require any special control signals or clock signals to operate the bidirectional bus. Thus, an SoC employing the present invention can be truly scalable since any number of modules can be added to the bidirectional bus without reconfiguring the bus structure.
A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.